2015年6月19日，anysilicon
Integrated circuit (IC) designers are learning that a technique long used on older process nodes is providing even more valuable benefits as they develop devices to be manufactured at advanced technology nodes, including 28nm and beyond. During a period when it takes $10 million or more to bring a device to market, focused ion beam (FIB) circuit edit has become strategically important tool for reducing costs, optimizing performance and functionality, mitigating risk, and speeding time to market for complex device designs.
它被广泛了解，IC设计人员会遇到很多新的问题，在这将是困难的先进工艺节点，如果不是不可能的，根据以往的设计工作预期。EDA工具提供商都已经解决的先进节点设计与咨询各地的设计流程等方式来处理大量的技术挑战的难度。除了应用这些新的设计流程的修改，开发者也可以申请FIB电路编辑犯下成本高或全光罩的冗长的时间表之前调试和验证修复或探索优化设计变化的过程中。
Design success barriers are magnified at advanced process nodes, where mask costs are high and it is more difficult to find and fix bugs. It is widely understood that designers will encounter many new problems at advanced process nodes that would be difficult, if not impossible, to anticipate based on previous design work. The feature sizes of chips manufactured at 20nm process nodes are 10 times smaller than the wavelength of the laser light typically used in lithography. Pre-silicon testing is growing extremely tedious, simulation times are growing excessive, and many designs simply cannot be 100 percent verified. Simulation models may be imperfect for extremely complex designs, and packaging can cause stresses to sensitive devices.
在从多次图案化此环境范围的挑战和布局依赖效应（LDE）于使用局部互连层。设计和集成的复杂性上升到与每个新技术节点上新台阶。服务器信号和电源的电迁移也产生挑战。降低金属间距导致耦合效应和信号完整性问题。增加导线和通孔电阻，需要更先进的和可变的线的尺寸和逐渐变细的技术。此外，提取，时序，信号完整性分析和建模带来的变化的问题众多，设计师必须解决之前，他们可以在不牺牲性能，精确度。在20纳米光刻技术的局限性往往需要固定实现签收的很大。最后，设计人员面临众多的芯片和IP融合的挑战，是包装问题，以及额外的复杂性，因为这些问题的相互作用。
Similar challenges face designers of power control ICs and devices that combine control with power FET functionality. In these design environments, FIB circuit edit techniques similarly provide benefits at advanced process nodes, and will be increasingly important as many power devices move to silicon carbide (SiC), gallium nitride (GaN), and other wide badgap materials.
Many EDA tool providers are already addressing these issues with advice around design flow and other ways to handle numerous technical challenges. This isn’t sufficient, however. In addition to applying new design flow modifications, developers can also apply FIB circuit editing with their early prototypes during de-bug. The same techniques can also be used to explore design optimization opportunities, by quickly and inexpensively implementing and creating physical prototypes that can be tested and validated before committing to the high cost or lengthy timetables of a full mask spin. FIB-edited device prototypes can be used to guide one-time modifications to masks, eliminating the need for a trial-and-error approach with successive versions of masks.
FIB systems have a number of uses in the semiconductor industry, microelectromechanical system fabrication, and biological studies. A primary use of FIB systems in the semiconductor industry is for circuit edit, allowing designers to cut traces or add metal connections within a chip (see FIg. 1). FIB edits can be performed quickly and easily, at a small fraction of the $5 million to $10 million in costs that are typical for a new lot of wafers in a fab. Using today’s state-of-the-art equipment, it is possible to edit circuits fabricated with 28 nm and smaller technology nodes that feature multiple layer metal stacks and occupy flip chip and other advanced chip scale form factors.
图1：多个连接和切口示出了用于前侧FIB电路编辑。
FIB电路编辑使用细微聚焦镓（Ga +）具有纳米级分辨率的离子束进行。是可能的图像蚀刻和存款材料上的IC，具有相当高的水平的精度。通过去除和沉积材料，FIB电路编辑使得设计者能够切割和连接电路的实时装置内，并为电测试创建探测点。它是在IC器件执行显微的等价物。贯通导体高能GA +束可磨，使用不同类型的气体的要么提高研磨精度或更有效地沉积导电和电介质材料。例如，通过使用适当的气体化学物质，钨，铂，或二氧化硅的选择可以非常精确地使用离子束沉积。
In order to perform circuit edits, the FIB tool is coupled to a CAD navigation system that makes it possible to locate the area of interest. FIB circuit edit typically uses the designer’s GDS files to navigate to the precise area. This provides a method to find subsurface features and ensuring that the right edits are made (see Fig. 2). Accurate beam positioning is one of the most critical requirements for FIB circuit edit.
图2. CAD布局被用于执行FIB电路编辑。
There are many uses for FIB circuit edit at every commercially available node. It can be used both to verify design change on the tester, and to validate design change at the system board level. Typical applications include:
Fig. 3 shows the best approach for integrating FIB circuit edit into the overall IC development and testing process.
Fig. 3: FIB circuit edit can be inserted both at the simulation stage and later during de-bug to optimize success rates during the IC design process.
在功率半导体领域，大多数电流控制产品都采用传统的硅工艺制造，并且因为它是与任何其他模拟或数字电路与这些设备中几乎相同的方式被执行FIB电路编辑。在未来，有一个很大的可能性，司机将移动宽带隙材料。FIB电路编辑应该提供这些设备的好处，以及。的SiC，GaN和其它宽禁带半导体材料使功率半导体器件能够承受高电压和温度，同时提供更高的频率响应，增加的电流密度，以及更快的开关速度。与此同时，然而，相关的设计和特性，过程监控和可靠性，他们目前复杂的挑战。挑战变得更加困难，在先进工艺节点。
有一种比较普遍的误解，认为FIB电路编辑只在90nm和65nm工艺节点上运行良好，并且已低于任何“运行的天然气”。这是不正确的。由于已经从运行数以千计的电路编辑小时/月的专业团队的经验中获得的工具和方法的进步，FIB电路编辑现在可以用于更精确的光束引导，同时在在小范围内进行操作，执行更复杂的操作背部和该装置的前侧，并且手柄的铜层。
对于FIB电路编辑的一个主要发展领域是工具，为小切口作为解决方案的一部分提供更好的纵横比的能力。FIB系统继续在诸如离子束分辨率，操作软件和CAD导航领域得益于更大的收益交付给进步。离子束分辨率的进步，独自一人，已经交付已识别的小功能，在视觉效果指点帮助，实现精确定位CAD，提高箱位置精度的关键显著的新功能。图已经从2008年实现了本图4示出的分辨率的进步。
图4：在左侧示出了图像位线上的90nm工艺在2008年，今日在右侧示出了该图像获得子25nm的器件的位线，而。[照片DCG系统的礼貌。
Tool advances are only part of the story, however. Because FIB tools are not entirely automated, there is no under-estimating the critical importance of FIB operator experience to circuit edit success. For example, endpoint detection, or the ability to know when selected layers of interest have been successfully etched, continues to require a high level of skill in order to achieve high success rates. Operator skill in this area is even more important at smaller geometries, and during particularly challenging FIB operations. Also important is the unique operator knowledge in such areas as IC circuitry, IC process technology, ion milling patterns, and general FIB tool usage basics.
Achieving this expertise can be difficult for an in-house operation. Often, larger semiconductor companies who already conduct some level of circuit edit will augment these resources with external service labs that have deeper and more extensive experience in solving the toughest FIB circuit edit challenges. As for small- and mid-sized companies, few can bear the expense of purchasing a FIB tool that might cost $1 million or more. Even if they could afford the tool, it would be difficult to staff a team with the necessary experience to most effectively operate it. Most companies of this size tend to go directly to an external lab that can implement circuit edits to support basic electrical design characterization or verification of redesign parameter, and offers a full range of debug tools necessary for solving difficult logic failures and other anomalies.
有用于FIB电路编辑的成就，其中包括众多的先决条件：
![高分辨率挖沟使编辑在先进制程节点。[图像FIB国际公司的礼貌]](http://www.eag.com/cmss_files/attachmentlibrary/fib-circuit-edit-fig-7.JPG "FIB Circuit Edits at advanced nodes")
图7：高分辨率挖沟使编辑在先进制程节点。FIB国际公司的[图像礼貌IC设计验证和确认将继续在难度增加，因为该行业向下移动纳米尺度几何曲线。虽然有些人可能认为，FIB电路编辑是在当今先进节点过时了，它实际上成为改进这些设计，而这往往耗资千万$以上为市场带来的成功率越来越有价值。由于这两个工具的技术和最佳实践的进步，FIB电路编辑可在先进节点可用于多种用途，包括调试和验证修复，以及在过程的早期探索设计优化的机会，而无需承诺昂贵和费时的全光罩。
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This is a guest post byEAGthat provides semiconductor and electronics design firms worldwide with test, debug, and early engineering support.
