UK
在敏捷模拟我们已经汇集了球队行业资深人士从模拟，IP和设计自动化的世界彻底改变模拟IP的开发和交付的方式。总部设在剑桥，我们正在成长迅速，成为全球领先的模拟IP公司之一。利用我们的创新技术，我们能够设计出模拟IP更快，以更高的质量，任何半导体工艺。随着我们最好的一流的成果，我们在扩大市场准入，以模拟IP中有利于客户的能力，开发创新的芯片设计的一种方式。
敏捷类似物是建立广泛的IP产品组合目标应用，包括物联网，安全，无线，AI，汽车和一般的SoC / ASIC的。我们的产品包括：ADC，DAC，LDO，带隙电压/电流参考，时钟/振荡器，温度传感器和比较器。我们在不断地扩大我们的产品组合，以满足客户对电源管理，传感器和数据转换器和时钟发生器模拟IP的需求。
敏捷模拟’s core technology allows us to re-generate our Analog IP according to our customers’ specifications quickly. This capability allows us to optimize our Analog IP in terms of power, performance and area (PPA) for each customer’s specific application requirements.
Our innovative design methodology is programmatic, systematic and repeatable leading to Analog IP that is more verifiable, more robust and more reliable than current solutions. Our team has extensive experience with advanced SoCs and ASICs and we understand the complexity involved in assembling a modern chip. This is why we provide best-in-class deliverables that are guaranteed to be consistent and of high quality, making our IP easy to use and minimizing integration time and effort for our customers.
雅居乐模拟的核心技术使我们能够重新生成任何进程我们的模拟IP。这种能力使我们的客户能够选择最适合自己的应用程序，而对IP供应受到限制的半导体工艺。
Our innovative design methodology is programmatic, systematic and repeatable leading to Analog IP that is more verifiable, more robust and more reliable than current solutions. Our team has extensive experience with advanced SoCs and ASICs and we understand the complexity involved in assembling a modern chip. This is why we provide best-in-class deliverables that are guaranteed to be consistent and of high quality, making our IP easy to use and minimizing integration time and effort for our customers.
敏捷模拟has a vast industry network and a number of strategic partnerships. We guide and connect our customers to the resources they need to successfully take a chip to market including: EDA, IP, Foundry, ASIC design, ESD, Packaging, and ATE (Assembly & Test) amongst others.
我们的团队拥有先进的SoC和ASIC包括混合信号，模拟，数字和射频组件的丰富经验。敏捷模拟利用这方面的知识，提供咨询，指导和系统级考虑，使我们的客户带来复杂的芯片大规模生产安全，可靠。
敏捷模拟is developing a portfolio of Power Management IP that can be configured to meet the differing requirements of various applications including IoT, HPC, Wireless, Automotive, AI and SoCs/ASICs. Our Power Management IP is available on any process and can be optimized for:
We are constantly adding new IP to our portfolio including:
敏捷模拟is developing a portfolio of Data Converter and Sensor IP for processing of both on-chip and off-chip signals. Our Data Converter and Sensor IP is customized to our customers’ needs and is available on any process.
We are constantly adding new IP to our portfolio including:
可编程阈值模拟比较器对电平检测和中断产生
敏捷模拟正在开发时钟产生和定时IP的组合对于片上时钟信号的产生。我们定时IP定制以满足客户的需求，并提供对任何进程。
We are constantly adding new IP to our portfolio including:
Key Features
The agileADC GP analog-to-digital converter is a configurable general purpose ADC that uses a traditional Charge-Redistribution SAR architecture referenced to VDD, VSS. The architecture is capable of achieving up to 12-bit resolution at sample rates up to 5 Msps. It includes an eight-channel input multiplexor. The ADC provides input buffers that may also be bypassed for full rail-to-rail capability.
The agileADC GP analog-to-digital converter can be tuned to your specifications and is ideally suited for signal conversion and monitoring in applications such as in IoT, Security, Automotive, AI and general SoCs and ASICs.
敏捷模拟设计是基于尝试和测试架构，以确保可靠性和功能性。我们的设计方法是纲领性的，系统的和可重复的领先模拟IP是比较可验证的，更健壮，更可靠。我们的方法还使我们能够迅速重新定位我们的IP不同的工艺方案。所述agileADC GP模拟数字转换器可以用CMOS和FD-SOI工艺从180nm向下到22nm。
Key Features
The agileDAC GP is a digital-to-analog converter that uses a traditional capacitive DAC architecture. The agileDAC can either be referenced to the supply voltage or to an external reference voltage. The architecture is capable of achieving up to 8-bit resolution at sample rates up to 500 ksps.
所述agileDAC GP数位类比转换器适合于信号转换和在应用，如在的IoT，安全，汽车，AI和一般的SoC和ASIC驱动。
我们的设计方法是纲领性的，系统的和可重复的领先模拟IP是比较可验证的，更健壮，更可靠。我们的方法还使我们能够迅速重新定位我们的IP不同的工艺方案。The agileDAC GP digital-to-analog converter is available on CMOS and FD-SOI processes from 180nm down to 22nm.
Key Features
The agileLDO GPD is a linear low-dropout voltage regulator (LDO) providing precision and programmable voltage regulation across a wide range of input and output voltages. The regulator architecture provides a high dynamic performance making it suitable for digital applications.
该agileLDO GPD中的应用，如物联网，安全，汽车，AI和一般的SoC和ASIC适用于数字内核。
敏捷模拟设计是基于尝试和测试架构，以确保可靠性和功能性。我们的设计方法是纲领性的，系统的和可重复的领先模拟IP是比较可验证的，更健壮，更可靠。我们的方法还使我们能够迅速重新定位我们的IP不同的工艺方案。所述agileLDO GPD低压降稳压器可以用CMOS和FD-SOI工艺从180nm向下到22nm。
