Korea
我们是专门用于视频处理的硅IP供应商。我们由15年以上的经验丰富的ASIC设计工程师，并取得了多媒体SOC，ISP和视频IP核。
Several customers use our IP and many chips designed by us. We will provide you with high performance compact IP and professional support.
H.265 Encoder / Decoder IP up to 8K 30fps
H.264 Encoder / Decoder IP up to 8K 30fps
IP规范
• H.264 Encoder High profile
• H.264 Decoder : Self encoded stream decoder
•ASIC级编码效率
• Zero delay optimized : Under 3ms up to 8K encoding
• Max resolution : YUV 4:2:0, Expandable up to 8K
• Max perfomance
1920×1088 60 fps UltraScale+ Kintex
4096×2160 60 fps UltraScale+ Virtex
8196×4320 60 fps ASIC
• Compact Logic Size
• Optimized system bus bandwidth
Encoding Tools
• Macro-block 16×16 / 8×8 / 4×4 all estimation
• Intra prediction 0 ~ 8 all support
• Wide motion search range (+-96, +-48) for Moving application
• 1/4 sub-pel motion search
•IPPP 1个参考帧
• Deblock filtering
• Multi-slice encoding support
• De-quant for ROI image enhancement
JPEG Encoder / Decoder IP
IP规范
• JPEG Base Profile support
•格式
Decoder : YUV444 / YUV422 / YUV420 8-bit support
Encoder : YUV422 / YUV420 8-bit support
• 解析度
up to 4240×2832 (Expandable with multi core processing)
• Performance (Decoder estimated)
1-core 1920×1080 6~7fps @ 120Mhz
9-core 1920×1080 60fps @ 120Mhz
• FPGA Utilization
1-core : Xilinx Logic Cell 12,558 (7.74% of 160T)
9-core : Xilinx Logic Cell 113,025 (70% of 160T)
• Mass production for several ASIC process as 90nm, 65nm, 40nm
无损帧缓存压缩IP
IP规范
• Lossless compression for bus bandwidth reduction
• Typical 45% (min 25% ~ max 75%) bandwidth reduction
• Flexible specification with scalable and customisable design
✓ YUV420 1080P 30fps at 120Mhz : compression IP 53K gate count decompression IP 27K gate count
✓YUV420 2160P 30fps的在240MHz的：压缩IP 84K门数减压IP 54K门数
✓ Bayer 14bit 1080P 30fps at 120Mhz : compression IP 92K gate count decompression IP 47K gate count
✓拜耳14bit的2160P 30fps的在240MHz的：压缩IP 147K门数减压IP 94K门数
Multiple camera image stitching IP
Specification
• 1 Channel : Lens distortion correction
• Up to 24 multi channel image stitching for 360 degree panoramic image
• YUV 420 8-bit and any resolution format support
• 2D or Stereo alignment for 3D 360
• Equirectangular / Top Bottom 3D format output
• Filtering and smoothing for seamless image
多个源信道之间为HDR•混合ISP差
•兰德om rotation and warping at each pixel for any camera rig support
• Stitching optimized smart cache controller
• 3840×1920 60 fps at 425 Mhz for ASIC
3840×1920 60 fps at 120 Mhz for FPGA
• Scalable and expandable design for performance upgrade
•带宽减少在与MnHEVC飞/ MnHTC编码器IP
• Application : Drone / ADAS / VR Camera / Robot / Military / Boring Cam
Delivery
• Technical documentation
•拼接调整S / W工具
• Firmware to control H/W IP
• Verilog RTL source code and testbench
Short wave IR ISP IP
AXI chip to chip between ASIC or FPGA
